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Dr. Shivam Verma
Assistant Professor
Department of Electronics Engineering
extension: 7165437
Area of Interest: 
Spintronics, Devices and Circuits for VLSI, Non-volatile memory and logic circuits


Ph.D. (Microelectronics and VLSI) 
Dissertation: Design of Spin Transfer Torque Based Memory and Logic,
Indian Institute of Technology, Roorkee, 2017.

M. Tech. (with Hons.),
Specialization: Microelectronics, 
Indian Institute of Technology (BHU), Varanasi, 2012.

B. E. (Electronics and Communication Engineering),
Shri Vaishnav Institute of Technology and Science, Indore, M.P, 2010

Journal Articles:
  1. Shivam Verma, Shalu Kaundal, and Brajesh Kumar Kaushik, “Modeling of In-Plane Magnetic Tunnel Junction for Mixed Mode Simulations,” IEEE Trans. on Magnetics, vol. 50, no. 8, Mar. 2014.
  2. Shivam Verma, Shalu Kaundal, and Brajesh Kumar Kaushik, “Novel 4F2 Buried Source Line STT MRAM Cell with Vertical GAA Transistor as Select Device,” IEEE Trans. on Nanotechnology, vol. 13, no. 6, pp. 1163–1171, 2014.
  3. Shivam Verma, M. Satyanarayana Murthy, and Brajesh Kumar Kaushik, “All Spin Logic (ASL): A Micromagnetic Perspective,” IEEE Trans. on Magnetics, vol. 51, no. 10, pp. 3400710-1–3400710-7, 2015.
  4. Shivam Verma, and Brajesh Kumar Kaushik, “Low Power High Density STT MRAMs on 3D Vertical Silicon Nano-wire Platform,” IEEE Trans. on VLSI Systems, vol. 24, no. 4, pp. 1371–1376, 2015.
  5. Shivam Verma, Pankaj Kumar Pal, Sanjay Mahawar, and Brajesh Kumar Kaushik, “Performance Enhancement of STT MRAM Using Asymmetric-k Sidewall-spacer NMOS,” IEEE Trans. on Electron Devices, vol. 63, no. 7, pp. 2771–2776, 2016.
  6. Shivam Verma, Anant. A. Kulkarni, and Brajesh Kumar Kaushik, “Spintronics based Devices to Circuits: Perspectives and Challenges,” IEEE Nanotechnology Magazine, vol. 10, no. 4, pp. 13-28, 2016.
  7. A Kulkarni, S Prajapati, Shivam Verma, and  Brajesh Kumar Kaushik, “Optimal Boolean Logic Quantum Circuit Decomposition for Spin-Torque-Based n-Qubit Architecture,” IEEE Trans. on Magnetics, vol. 54, no. 10, Oct. 2018.
  8. S. Prajapati, Shivam Verma, A. A. Kulkarni, and Brajesh Kumar Kaushik, “Modeling of magnetic tunnel junction for multilevel STT-MRAM cell,” IEEE Trans. on Nanotechnology (Early access).


  • Sanjay Mahawar, Shivam Verma, Pankaj Kumar Pal, and Brajesh Kumar Kaushik, “High Reliability STT MRAM using Fully Depleted Body and 4H–SiC Buried Oxide NMOS,” in Proc. IEEE 11th International Conference on Electron Devices & Solid-State Circuits (EDSSC 2015), Singapore, pp. 705-708, June 1-4, 2015.
  • Shivam Verma, Sanjay Mahawer, and Brajesh Kumar Kaushik, “Low Power STT MRAM Cell With Asymmetric Drive Current Vertical GAA Select Device,” in Proc. 12th IEEE International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON 2015), Hua Hin, Thailand, pp. 1-5, June 24-27, 2015.
  • Sanjay Prajapati, Shivam Verma, Anant Aravind Kulkarni, and Brajesh Kumar Kaushik, “Novel compact model for multi-level spin torque magnetic tunnel junctions,” in Proc. SPIE 9931, Spintronics IX, San Diego, CA, USA, August 28, 2016.


  • B. K. Kaushik and Shivam Verma, Spin Transfer Torque Based Devices Circuits and Memory, Artech Press, Norwood, MA, USA, 2016.
  • B. K. Kaushik, Shivam Verma, Anant Kulkarni, and Sanjay Prajapati, Next Generation Spin Torque Memories, Springer Nature, USA, 2017.
Title of Workshop Dates Sponsoring Agency No. of External Participants No. of External Participants
Nanoscale devices and circuits 17 to 22 June 2019 E & ICT Academy NIT Warangal 30 5


Name of Student Thesis Title Status
Cherala Sagar Design converging challenges by meeting timing, area and power at lower technology nodes  Completed
Suryaprakashrao Paidi  Design of  Clock Distribution Cell for Microprocessor System Completed

I have attended the following workshops and programmes
1) Two phase 4-week Induction Training Programme for Newly Recruited Assistant Professors of NIT Warangal dealing with Teaching and Pedagogy
2) 1 day AMS- Analog IC Design workshop on 31 August 2018 at AMS Hyderabad
3) One day National Workshop on " Role of IPR in Innovation Management for Academia – Industry Collaboration ", November 17, 2018 at NIT Warangal
4)  Session chair in IEEE International Conference on Modeling of Circuits, Systems and Devices (MOS AK India 2019) from 25-27 February 2019 at IIT Hyderabad.
5) TPC member of IEEE VDAT-2019, IEEE UPCON-2019, and Exhibition co-chair in IEEE MOS-AK India 2019.

  • IEEE Transaction of Electron Devices
  • IEEE Transaction of Circuits and Systems Brief
  • IEEE Transaction of Magnetics
  • IEEE Transaction on Nanotechnology
  • Microelectronic Journal, Elsevier
  • Assistant Professor in the Department of Electronics Engineering, IIT (BHU), Varanasi since 27th August 2019
  • Assistant Professor in ECE Department, NIT Warangal, India from June 2018 to August 2019
  • Assistant Professor in EEE Department, BITS PIlani, K. K. Birla Goa Campus, Goa, India from May 2017 to May 2018
Sl. No. Title Funding Agency Amount Sanctioned
(INR In Lakhs
Scheme Status
1. Development of Simulation Software for Spintronic Device and Circuit Simulation SERB  16.13 Start-up Research Grant Ongoing